In digital serial communication protocols, a maximum delay may be imposed between a clock edge and a data transition (i.e., switch). A digital buffer circuit, used for transitioning between two different voltage domains, may contribute significantly to the delay between a clock edge and a data transition. The digital buffer circuit includes an output stage with transistors for switching between an upper rail and a lower rail of an output voltage domain according to the data transitions of an input voltage domain. The transistors in an output stage are designed in accordance with a maximum output voltage that the digital buffer circuit is expected to experience. The switching speeds of these transistors are reduced; however, as the output voltage is lowered from this maximum voltage.